Mar 09 09:37:29.176 VTTY: Console port: waiting connection on tcp port 2001 for protocol IPv4 (FD 11)
Mar 09 09:37:29.192 slot0: C/H/S settings = 0/4/32
Mar 09 09:37:29.193 slot1: C/H/S settings = 0/4/32
Mar 09 09:37:29.495 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,idle_pc=0x60aa5f14,JIT on)
Mar 09 09:37:29.495 CPU0: CPU_STATE: Starting CPU (old state=2)...
Mar 09 09:37:29.578 ROM: Microcode has started.
Mar 09 09:37:29.581 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:37:29.583 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xffffffff80a9d228 (size=1)
Mar 09 09:37:29.583 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80a9d23c (size=1)
Mar 09 09:37:29.669 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x6026eef8 (size=2)
Mar 09 09:37:29.670 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60276800 (size=2)
Mar 09 09:37:29.670 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc=0x60276810 (size=2)
Mar 09 09:37:29.670 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007dac,a2=0x00000010,a3=0xbfb00000)
Mar 09 09:37:30.242 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:37:30.271 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x60283d28 (size=2)
Mar 09 09:37:30.272 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c50: bus=0,device=0,function=0,reg=0x00
Mar 09 09:37:30.272 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c54: bus=0,device=0,function=0,reg=0x00
Mar 09 09:37:30.272 CPU0: PCI: read request for device 'gt96100' at pc=0x60286a04: bus=0,device=0,function=0,reg=0x08
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x04
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x04
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x84
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x84
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:37:30.272 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:37:30.273 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=0x6028436c (size=2)
Mar 09 09:37:30.273 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:37:30.273 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:37:30.273 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:30.273 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:37:30.273 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:37:30.273 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:37:30.273 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x00
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x00
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x18
Mar 09 09:37:30.274 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x18
Mar 09 09:37:30.274 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x20
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x20
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x24
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x24
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x68
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x68
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x00
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x00
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x18
Mar 09 09:37:30.274 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x18
Mar 09 09:37:30.274 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x20
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x20
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x24
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x24
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x30
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x40
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x64
Mar 09 09:37:30.274 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x68
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x68
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:37:30.275 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x00
Mar 09 09:37:30.275 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x00
Mar 09 09:37:30.275 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x40
Mar 09 09:37:30.275 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x40
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x18
Mar 09 09:37:30.275 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x18
Mar 09 09:37:30.275 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x20
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x20
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x24
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x24
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x30
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x30
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x40
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x40
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x64
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x64
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x68
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x68
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:37:30.275 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:37:30.275 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60276b14 (size=2)
Mar 09 09:37:32.728 ROM: unhandled syscall 0x0000003e at pc=0x60a9e9bc (a1=0x80007d9c,a2=0x00002580,a3=0x64590000)
Mar 09 09:37:32.728 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007da4,a2=0x00000000,a3=0x64590000)
Mar 09 09:37:33.360 CPU0: JIT: partial JIT flush (count=178)
Mar 09 09:37:33.408 CPU0: JIT: flushing data structures (compiled pages=234)
Mar 09 09:37:33.452 ROM: trying to read bootvar 'BOOT'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'CONFIG_FILE'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'BOOTLDR'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'RSHELF'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'DSHELF'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'DSHELFINFO'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'RESET_COUNTER'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'CHRG_LOCRECSN'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'CHRG_ID'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'SLOTCACHE'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'OVERTEMP'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'DIAG'
Mar 09 09:37:33.452 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:37:33.469 CPU0: JIT: partial JIT flush (count=180)
Mar 09 09:37:33.552 CPU0: JIT: flushing data structures (compiled pages=242)
Mar 09 09:37:33.617 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60819334 (size=2)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60818f30 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f74 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f80, value=0x00000020 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f84 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f8c, value=0x00000000 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f98 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818fa4, value=0x00000040 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fb8 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fc4, value=0x00000000 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fd0 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fe0, value=0x00000080 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adac (size=1)
Mar 09 09:37:33.617 CPU0: MTS: write access to undefined address 0x3c000002 at pc=0x6081adb8, value=0x00000080 (size=1)
Mar 09 09:37:33.617 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adbc (size=1)
Mar 09 09:37:33.704 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:33.790 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:33.868 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:33.952 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:34.036 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:34.118 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c080007 at pc=0x608190cc, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c080008 at pc=0x608190d4, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c080009 at pc=0x608190dc, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c08000a at pc=0x608190e0, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c08000b at pc=0x608190e4, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: write access to undefined address 0x3c08000c at pc=0x608190e8, value=0x00000002 (size=1)
Mar 09 09:37:34.119 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60819f6c (size=1)
Mar 09 09:37:34.158 CPU0: JIT: partial JIT flush (count=187)
Mar 09 09:37:34.200 CPU0: JIT: flushing data structures (compiled pages=253)
Mar 09 09:37:34.253 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60283dd4 (size=2)
Mar 09 09:37:34.253 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000, pc=0x60283ddc (size=2)
Mar 09 09:37:34.411 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.411 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.475 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:37:34.475 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:37:34.475 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:34.475 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:37:34.475 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:37:34.475 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:37:34.475 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:37:34.476 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:37:34.625 CPU0: JIT: partial JIT flush (count=175)
Mar 09 09:37:34.731 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x60678648 (size=1)
Mar 09 09:37:34.731 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x60678650, value=0x00000004 (size=1)
Mar 09 09:37:34.734 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:34.734 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:34.734 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:34.734 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:34.734 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:34.734 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:34.735 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:34.735 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:34.738 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.738 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.739 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.739 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x14
Mar 09 09:37:34.739 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x14
Mar 09 09:37:34.739 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x04
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x04
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:37:34.739 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.739 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:37:34.739 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:37:34.747 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:34.747 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:34.747 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:34.773 CPU0: JIT: flushing data structures (compiled pages=277)
Mar 09 09:37:34.787 CPU0: IO_FPGA: read from unknown addr 0x4c, pc=0x60277d00 (size=2)
Mar 09 09:37:34.787 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0x0, pc=0x60277d08 (size=2)
Mar 09 09:37:34.787 CPU0: IO_FPGA: read from unknown addr 0x2e, pc=0x60277d28 (size=2)
Mar 09 09:37:34.787 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x40, pc=0x60277d38 (size=2)
Mar 09 09:37:34.792 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:34.792 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:34.793 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:34.795 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:34.795 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:34.795 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:34.795 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:34.795 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:34.795 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:34.796 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:34.796 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:34.800 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:34.800 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:34.800 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:34.822 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:37:34.867 CPU0: JIT: flushing data structures (compiled pages=281)
Mar 09 09:37:34.922 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:37:34.950 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:34.950 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:34.951 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:34.953 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:34.953 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:34.953 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:34.953 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:34.953 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:34.953 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:34.955 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:34.955 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:34.959 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:34.959 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:34.959 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:34.971 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:34.971 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:34.971 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.971 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.971 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:34.971 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:34.972 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:34.972 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:34.973 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:34.973 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:34.973 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:34.975 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:34.975 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:34.976 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:34.976 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:34.976 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:34.978 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:37:35.056 CPU0: JIT: partial JIT flush (count=202)
Mar 09 09:37:35.086 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:35.086 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:35.087 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:35.089 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:35.089 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:35.089 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:35.089 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:35.089 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:35.089 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:35.091 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:35.091 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:35.094 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:35.094 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:35.094 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:35.102 CPU0: JIT: flushing data structures (compiled pages=311)
Mar 09 09:37:35.297 CPU0: JIT: partial JIT flush (count=170)
Mar 09 09:37:35.335 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:37:35.392 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:37:35.438 CPU0: JIT: flushing data structures (compiled pages=310)
Mar 09 09:37:35.489 CPU0: JIT: partial JIT flush (count=203)
Mar 09 09:37:35.584 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:37:35.636 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:37:35.687 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:37:35.739 CPU0: JIT: partial JIT flush (count=190)
Mar 09 09:37:35.804 CPU0: JIT: flushing data structures (compiled pages=327)
Mar 09 09:37:35.878 CPU0: JIT: partial JIT flush (count=165)
Mar 09 09:37:36.052 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:37:36.107 CPU0: JIT: partial JIT flush (count=190)
Mar 09 09:37:36.443 CPU0: JIT: flushing data structures (compiled pages=555)
Mar 09 09:37:36.472 ROM: trying to read bootvar 'PMDEBUG'
Mar 09 09:37:36.483 ROM: trying to read bootvar 'MONDEBUG'
Mar 09 09:37:36.531 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:37:36.770 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:37:36.914 CPU0: JIT: partial JIT flush (count=194)
Mar 09 09:37:37.002 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:37:37.044 CPU0: JIT: partial JIT flush (count=213)
Mar 09 09:37:37.073 ROM: unhandled syscall 0x0000001a at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:37:37.073 ROM: unhandled syscall 0x00000009 at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:37:37.103 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:37:37.172 CPU0: JIT: partial JIT flush (count=194)
Mar 09 09:37:37.218 CPU0: JIT: flushing data structures (compiled pages=564)
Mar 09 09:37:37.260 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:37:37.306 CPU0: JIT: flushing data structures (compiled pages=553)
Mar 09 09:37:37.376 CPU0: JIT: partial JIT flush (count=184)
Mar 09 09:37:37.470 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:37:37.579 CPU0: JIT: partial JIT flush (count=189)
Mar 09 09:37:37.642 CPU0: JIT: flushing data structures (compiled pages=556)
Mar 09 09:37:37.707 CPU0: JIT: partial JIT flush (count=192)
Mar 09 09:37:37.748 CPU0: JIT: flushing data structures (compiled pages=561)
Mar 09 09:37:37.794 CPU0: JIT: partial JIT flush (count=205)
Mar 09 09:37:37.839 CPU0: JIT: flushing data structures (compiled pages=561)
Mar 09 09:37:37.894 CPU0: JIT: partial JIT flush (count=208)
Mar 09 09:37:37.946 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:37:37.995 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:37.995 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:37.996 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:37.998 CPU0: JIT: partial JIT flush (count=206)
Mar 09 09:37:38.003 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:37:38.003 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:37:38.003 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:37:38.003 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:37:38.003 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:37:38.003 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:37:38.006 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:37:38.006 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:37:38.035 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:37:38.075 CPU0: JIT: partial JIT flush (count=208)
Mar 09 09:37:38.098 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:37:38.098 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:37:38.098 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:37:38.098 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:37:38.098 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:37:38.098 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:37:38.099 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:37:38.099 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:37:38.109 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:37:38.155 CPU0: JIT: partial JIT flush (count=203)
Mar 09 09:37:38.189 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:37:38.226 CPU0: JIT: partial JIT flush (count=211)
Mar 09 09:37:38.264 CPU0: JIT: flushing data structures (compiled pages=563)
Mar 09 09:37:38.311 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:37:38.331 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:37:38.331 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:37:38.331 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:37:38.345 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:37:38.385 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:37:38.425 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:37:38.516 CPU0: JIT: partial JIT flush (count=188)
Mar 09 09:37:38.577 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:37:38.599 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608192f4 (size=2)
Mar 09 09:37:38.599 CPU0: IO_FPGA: write to unknown addr 0x16, value=0x1, pc=0x608192fc (size=2)
Mar 09 09:37:38.610 ROM: trying to read bootvar 'ROM_PERSISTENT_UTC'
Mar 09 09:37:38.623 CPU0: JIT: partial JIT flush (count=192)
Mar 09 09:37:38.691 CPU0: JIT: flushing data structures (compiled pages=570)
Mar 09 09:37:38.737 CPU0: JIT: partial JIT flush (count=197)
Mar 09 09:37:38.783 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:37:38.876 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:38.878 CPU0: JIT: partial JIT flush (count=187)
Mar 09 09:37:39.022 CPU0: JIT: flushing data structures (compiled pages=575)
Mar 09 09:37:39.067 CPU0: JIT: partial JIT flush (count=196)
Mar 09 09:37:39.102 CPU0: JIT: flushing data structures (compiled pages=571)
Mar 09 09:37:39.139 CPU0: JIT: partial JIT flush (count=218)
Mar 09 09:37:39.162 ROM: trying to set bootvar 'BSI=0'
Mar 09 09:37:39.165 ROM: trying to read bootvar 'RET_2_RCALTS'
Mar 09 09:37:39.165 ROM: trying to set bootvar 'RET_2_RCALTS='
Mar 09 09:37:39.180 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:37:39.205 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:39.240 CPU0: JIT: partial JIT flush (count=177)
Mar 09 09:37:39.251 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:37:39.358 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:39.447 CPU0: JIT: flushing data structures (compiled pages=574)
Mar 09 09:37:39.572 CPU0: JIT: partial JIT flush (count=182)
Mar 09 09:37:39.649 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:40.251 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:40.807 CPU0: JIT: flushing data structures (compiled pages=570)
Mar 09 09:37:40.866 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:41.277 CPU0: JIT: partial JIT flush (count=210)
Mar 09 09:37:41.410 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:42.013 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:42.613 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:43.199 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:43.619 CPU0: JIT: flushing data structures (compiled pages=580)
Mar 09 09:37:43.755 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:44.358 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:44.911 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:45.512 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:46.000 CPU0: JIT: partial JIT flush (count=208)
Mar 09 09:37:46.129 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:46.709 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:47.340 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:47.913 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:48.519 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:49.106 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:49.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:50.164 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:50.285 CPU0: JIT: flushing data structures (compiled pages=578)
Mar 09 09:37:50.505 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:50.885 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:51.285 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:51.749 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:52.129 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:52.529 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:52.929 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:53.461 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:53.950 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:54.550 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:55.152 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:55.752 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:56.353 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:56.954 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:57.554 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:58.185 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:58.785 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:59.386 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:37:59.986 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:00.376 CPU0: JIT: partial JIT flush (count=188)
Mar 09 09:38:00.593 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:01.202 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:01.773 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:02.405 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:03.005 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:03.575 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:04.176 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:04.806 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:05.379 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:05.979 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:06.549 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:07.180 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:07.780 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:08.352 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:08.952 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:09.583 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:10.154 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:10.754 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:11.355 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:11.955 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:12.556 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:13.075 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:13.646 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:14.247 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:14.847 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:15.447 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:16.018 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:16.266 CPU0: JIT: flushing data structures (compiled pages=576)
Mar 09 09:38:16.679 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:17.248 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:17.856 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:18.457 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:19.058 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:19.658 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:20.261 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:20.861 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:21.431 CPU0: JIT: partial JIT flush (count=190)
Mar 09 09:38:21.464 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:22.071 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:22.680 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:23.281 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:23.882 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:24.485 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:38:24.673 C3745_STOP: stopping simulation.
Mar 09 09:38:24.673 CPU0: CPU_STATE: Halting CPU (old state=0)...
Mar 09 09:38:24.758 DEVICE: Removal of device WIC-1T(0), fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.758 VM: shutdown procedure engaged.
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "slot1"
Mar 09 09:38:24.758 DEVICE: Removal of device slot1, fd=-1, host_addr=0x0, flags=2
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "slot0"
Mar 09 09:38:24.758 DEVICE: Removal of device slot0, fd=-1, host_addr=0x0, flags=2
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "ns16552"
Mar 09 09:38:24.758 DEVICE: Removal of device ns16552, fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "mem_bswap"
Mar 09 09:38:24.758 DEVICE: Removal of device mem_bswap, fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "rom"
Mar 09 09:38:24.758 DEVICE: Removal of device rom, fd=14, host_addr=0xed6c0000, flags=1
Mar 09 09:38:24.758 MMAP: unmapping of device 'rom', fd=14, host_addr=0xed6c0000, len=0x200000
Mar 09 09:38:24.758 VM_OBJECT: Shutdown of object "ram"
Mar 09 09:38:24.758 DEVICE: Removal of device ram, fd=13, host_addr=0xed8c0000, flags=34
Mar 09 09:38:24.758 MMAP: unmapping of device 'ram', fd=13, host_addr=0xed8c0000, len=0x10000000
Mar 09 09:38:24.847 VM_OBJECT: Shutdown of object "gt96100"
Mar 09 09:38:24.847 DEVICE: Removal of device gt96100, fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.847 VM_OBJECT: Shutdown of object "io_fpga"
Mar 09 09:38:24.847 DEVICE: Removal of device io_fpga, fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.847 VM_OBJECT: Shutdown of object "ssa"
Mar 09 09:38:24.847 DEVICE: Removal of device ssa, fd=12, host_addr=0xfd8c0000, flags=2
Mar 09 09:38:24.847 MMAP: unmapping of device 'ssa', fd=12, host_addr=0xfd8c0000, len=0x7000
Mar 09 09:38:24.847 VM_OBJECT: Shutdown of object "remote_ctrl"
Mar 09 09:38:24.847 DEVICE: Removal of device remote_ctrl, fd=-1, host_addr=0x0, flags=0
Mar 09 09:38:24.847 VM: removing PCI busses.
Mar 09 09:38:24.847 VM: deleting VTTY.
Mar 09 09:38:24.847 VTTY: Console port: closing FD 11
Mar 09 09:38:24.848 VM: deleting system CPUs.
Mar 09 09:38:24.848 CPU0: CPU_STATE: Halting CPU (old state=1)...
Mar 09 09:38:24.853 VM: shutdown procedure completed.
Mar 09 09:38:24.867 VM: trying to shutdown an inactive VM.