Mar 09 09:28:02.525 VTTY: Console port: waiting connection on tcp port 2003 for protocol IPv4 (FD 12) Mar 09 09:28:02.588 slot0: C/H/S settings = 0/4/32 Mar 09 09:28:02.588 slot1: C/H/S settings = 0/4/32 Mar 09 09:28:02.934 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,idle_pc=0x60aa5f14,JIT on) Mar 09 09:28:02.934 CPU0: CPU_STATE: Starting CPU (old state=2)... Mar 09 09:28:02.950 ROM: Microcode has started. Mar 09 09:28:02.950 ROM: trying to read bootvar 'WARM_REBOOT' Mar 09 09:28:02.950 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xffffffff80a9d228 (size=1) Mar 09 09:28:02.950 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80a9d23c (size=1) Mar 09 09:28:03.130 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x6026eef8 (size=2) Mar 09 09:28:03.131 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60276800 (size=2) Mar 09 09:28:03.132 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc=0x60276810 (size=2) Mar 09 09:28:03.132 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007dac,a2=0x00000010,a3=0xbfb00000) Mar 09 09:28:04.036 ROM: trying to read bootvar 'RANDOM_NUM' Mar 09 09:28:04.100 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x60283d28 (size=2) Mar 09 09:28:04.101 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c50: bus=0,device=0,function=0,reg=0x00 Mar 09 09:28:04.101 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c54: bus=0,device=0,function=0,reg=0x00 Mar 09 09:28:04.101 CPU0: PCI: read request for device 'gt96100' at pc=0x60286a04: bus=0,device=0,function=0,reg=0x08 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x04 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x04 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x84 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x84 Mar 09 09:28:04.101 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x0c Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x0c Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x8c Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x8c Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x10). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x10). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x90). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x90). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x14). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x14). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x94). Mar 09 09:28:04.102 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x94). Mar 09 09:28:04.102 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=0x6028436c (size=2) Mar 09 09:28:04.102 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:04.102 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:04.103 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:04.103 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x00 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x00 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x0c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x0c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x18 Mar 09 09:28:04.103 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x18 Mar 09 09:28:04.103 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x1c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x1c Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x20 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x20 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x24 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x24 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x30 Mar 09 09:28:04.103 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x30 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x3c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x3c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x64 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x64 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x68 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x68 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0xf0 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0xf0 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x00 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x00 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x0c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x0c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x18 Mar 09 09:28:04.104 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x18 Mar 09 09:28:04.104 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x1c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x1c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x20 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x20 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x24 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x24 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x30 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x30 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x3c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x3c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x64 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x64 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x68 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x68 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0xf0 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0xf0 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x00 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x00 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x0c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x0c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x18 Mar 09 09:28:04.104 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x18 Mar 09 09:28:04.104 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x1c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x1c Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x20 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x20 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x24 Mar 09 09:28:04.104 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x24 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x30 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x30 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x3c Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x3c Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x64 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x64 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x68 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x68 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0xf0 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0xf0 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.105 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.105 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60276b14 (size=2) Mar 09 09:28:07.691 ROM: unhandled syscall 0x0000003e at pc=0x60a9e9bc (a1=0x80007d9c,a2=0x00002580,a3=0x64590000) Mar 09 09:28:07.691 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007da4,a2=0x00000000,a3=0x64590000) Mar 09 09:28:08.755 CPU0: JIT: partial JIT flush (count=178) Mar 09 09:28:08.838 CPU0: JIT: flushing data structures (compiled pages=234) Mar 09 09:28:08.894 ROM: trying to read bootvar 'BOOT' Mar 09 09:28:08.894 ROM: trying to read bootvar 'CONFIG_FILE' Mar 09 09:28:08.894 ROM: trying to read bootvar 'BOOTLDR' Mar 09 09:28:08.894 ROM: trying to read bootvar 'RSHELF' Mar 09 09:28:08.894 ROM: trying to read bootvar 'DSHELF' Mar 09 09:28:08.894 ROM: trying to read bootvar 'DSHELFINFO' Mar 09 09:28:08.894 ROM: trying to read bootvar 'RESET_COUNTER' Mar 09 09:28:08.894 ROM: trying to read bootvar 'CHRG_LOCRECSN' Mar 09 09:28:08.894 ROM: trying to read bootvar 'CHRG_ID' Mar 09 09:28:08.894 ROM: trying to read bootvar 'SLOTCACHE' Mar 09 09:28:08.894 ROM: trying to read bootvar 'OVERTEMP' Mar 09 09:28:08.894 ROM: trying to read bootvar 'DIAG' Mar 09 09:28:08.894 ROM: trying to read bootvar 'WARM_REBOOT' Mar 09 09:28:08.915 CPU0: JIT: partial JIT flush (count=179) Mar 09 09:28:09.052 CPU0: JIT: flushing data structures (compiled pages=242) Mar 09 09:28:09.157 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60819334 (size=2) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c080022 at pc=0x60818f30 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f74 (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f80, value=0x00000020 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f84 (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f8c, value=0x00000000 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f98 (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818fa4, value=0x00000040 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c080023 at pc=0x60818fb8 (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fc4, value=0x00000000 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c080023 at pc=0x60818fd0 (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fe0, value=0x00000080 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081adac (size=1) Mar 09 09:28:09.158 CPU0: MTS: write access to undefined address 0x3c000002 at pc=0x6081adb8, value=0x00000080 (size=1) Mar 09 09:28:09.158 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081adbc (size=1) Mar 09 09:28:09.301 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.462 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.625 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.766 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.903 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:10.045 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c080007 at pc=0x608190cc, value=0x00000002 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c080008 at pc=0x608190d4, value=0x00000002 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c080009 at pc=0x608190dc, value=0x00000002 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c08000a at pc=0x608190e0, value=0x00000002 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c08000b at pc=0x608190e4, value=0x00000002 (size=1) Mar 09 09:28:10.045 CPU0: MTS: write access to undefined address 0x3c08000c at pc=0x608190e8, value=0x00000002 (size=1) Mar 09 09:28:10.046 CPU0: MTS: read access to undefined address 0x3c080022 at pc=0x60819f6c (size=1) Mar 09 09:28:10.104 CPU0: JIT: partial JIT flush (count=187) Mar 09 09:28:10.166 CPU0: JIT: flushing data structures (compiled pages=253) Mar 09 09:28:10.296 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60283dd4 (size=2) Mar 09 09:28:10.296 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000, pc=0x60283ddc (size=2) Mar 09 09:28:10.584 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.584 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.585 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.724 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:10.724 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:10.724 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.724 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.724 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.724 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:10.725 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:10.725 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:10.725 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:10.981 CPU0: JIT: partial JIT flush (count=175) Mar 09 09:28:11.158 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x60678648 (size=1) Mar 09 09:28:11.158 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x60678650, value=0x00000004 (size=1) Mar 09 09:28:11.161 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.161 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.161 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.161 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.161 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.161 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.163 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.163 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.166 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.166 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.167 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.167 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x14 Mar 09 09:28:11.167 NM-1FE-TX(1): registers are mapped at 0x4d000000 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x14 Mar 09 09:28:11.167 NM-1FE-TX(1): registers are mapped at 0x4d000000 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x04 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x04 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.167 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.167 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.167 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.179 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.179 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.179 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.217 CPU0: JIT: flushing data structures (compiled pages=277) Mar 09 09:28:11.235 CPU0: IO_FPGA: read from unknown addr 0x4c, pc=0x60277d00 (size=2) Mar 09 09:28:11.235 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0x0, pc=0x60277d08 (size=2) Mar 09 09:28:11.235 CPU0: IO_FPGA: read from unknown addr 0x2e, pc=0x60277d28 (size=2) Mar 09 09:28:11.235 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x40, pc=0x60277d38 (size=2) Mar 09 09:28:11.240 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.241 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.241 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.241 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.241 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.241 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.242 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.242 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.243 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.243 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.243 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.243 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.243 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.243 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.261 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.261 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.264 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.264 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.264 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.302 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:11.372 CPU0: JIT: flushing data structures (compiled pages=281) Mar 09 09:28:11.449 CPU0: JIT: partial JIT flush (count=200) Mar 09 09:28:11.487 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.487 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.487 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.487 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.487 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.487 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.488 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.488 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.490 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.490 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.490 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.490 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.490 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.490 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.493 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.493 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.497 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.497 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.497 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.511 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.511 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.512 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.512 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.513 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.513 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.513 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.516 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.516 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.517 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.517 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.518 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.518 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.519 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.522 CPU0: JIT: flushing data structures (compiled pages=308) Mar 09 09:28:11.652 CPU0: JIT: partial JIT flush (count=201) Mar 09 09:28:11.706 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.706 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.706 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.707 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.707 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.707 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.707 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.707 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.709 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.709 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.709 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.709 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.709 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.709 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.711 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.711 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.716 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.716 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.716 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.725 CPU0: JIT: flushing data structures (compiled pages=311) Mar 09 09:28:12.017 CPU0: JIT: partial JIT flush (count=165) Mar 09 09:28:12.085 CPU0: JIT: flushing data structures (compiled pages=308) Mar 09 09:28:12.163 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:12.228 CPU0: JIT: flushing data structures (compiled pages=310) Mar 09 09:28:12.320 CPU0: JIT: partial JIT flush (count=202) Mar 09 09:28:12.480 CPU0: JIT: flushing data structures (compiled pages=318) Mar 09 09:28:12.563 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:12.644 CPU0: JIT: flushing data structures (compiled pages=318) Mar 09 09:28:12.714 CPU0: JIT: partial JIT flush (count=189) Mar 09 09:28:12.799 CPU0: JIT: flushing data structures (compiled pages=327) Mar 09 09:28:12.926 CPU0: JIT: partial JIT flush (count=165) Mar 09 09:28:13.185 CPU0: JIT: flushing data structures (compiled pages=559) Mar 09 09:28:13.283 CPU0: JIT: partial JIT flush (count=189) Mar 09 09:28:13.944 CPU0: JIT: flushing data structures (compiled pages=555) Mar 09 09:28:13.977 ROM: trying to read bootvar 'PMDEBUG' Mar 09 09:28:13.993 ROM: trying to read bootvar 'MONDEBUG' Mar 09 09:28:14.075 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:14.478 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:14.717 CPU0: JIT: partial JIT flush (count=193) Mar 09 09:28:14.859 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:14.914 CPU0: JIT: partial JIT flush (count=213) Mar 09 09:28:14.953 ROM: unhandled syscall 0x0000001a at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023) Mar 09 09:28:14.953 ROM: unhandled syscall 0x00000009 at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023) Mar 09 09:28:14.996 CPU0: JIT: flushing data structures (compiled pages=557) Mar 09 09:28:15.088 CPU0: JIT: partial JIT flush (count=194) Mar 09 09:28:15.144 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:15.223 CPU0: JIT: partial JIT flush (count=215) Mar 09 09:28:15.294 CPU0: JIT: flushing data structures (compiled pages=552) Mar 09 09:28:15.347 CPU0: JIT: partial JIT flush (count=213) Mar 09 09:28:15.448 CPU0: JIT: flushing data structures (compiled pages=557) Mar 09 09:28:15.661 CPU0: JIT: partial JIT flush (count=180) Mar 09 09:28:15.770 CPU0: JIT: flushing data structures (compiled pages=557) Mar 09 09:28:15.887 CPU0: JIT: partial JIT flush (count=181) Mar 09 09:28:15.945 CPU0: JIT: flushing data structures (compiled pages=558) Mar 09 09:28:16.001 CPU0: JIT: partial JIT flush (count=213) Mar 09 09:28:16.078 CPU0: JIT: flushing data structures (compiled pages=555) Mar 09 09:28:16.146 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.199 CPU0: JIT: flushing data structures (compiled pages=559) Mar 09 09:28:16.295 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.359 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.359 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.359 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.359 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.359 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.360 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.360 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.360 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.362 CPU0: JIT: flushing data structures (compiled pages=565) Mar 09 09:28:16.369 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.369 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.369 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.369 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.369 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.369 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.372 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.372 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.421 CPU0: JIT: partial JIT flush (count=218) Mar 09 09:28:16.502 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.544 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.544 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.548 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.548 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.548 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.548 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.548 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.548 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.550 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.550 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.551 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.551 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.564 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.647 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:16.702 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.702 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.702 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.702 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.702 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.702 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.703 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.703 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.707 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.707 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.707 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.707 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.707 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.707 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.708 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.713 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.713 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.714 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.714 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.714 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.714 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.714 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.714 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.764 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:16.825 CPU0: JIT: partial JIT flush (count=211) Mar 09 09:28:16.879 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:16.943 CPU0: JIT: partial JIT flush (count=206) Mar 09 09:28:17.021 CPU0: JIT: flushing data structures (compiled pages=560) Mar 09 09:28:17.085 CPU0: JIT: partial JIT flush (count=205) Mar 09 09:28:17.106 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:17.106 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:17.106 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:17.131 CPU0: JIT: flushing data structures (compiled pages=565) Mar 09 09:28:17.201 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:17.234 ROM: trying to read bootvar 'RANDOM_NUM' Mar 09 09:28:17.262 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:17.333 CPU0: JIT: partial JIT flush (count=217) Mar 09 09:28:17.410 CPU0: JIT: flushing data structures (compiled pages=576) Mar 09 09:28:17.493 CPU0: JIT: partial JIT flush (count=194) Mar 09 09:28:17.603 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:17.688 CPU0: JIT: partial JIT flush (count=196) Mar 09 09:28:17.762 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:17.892 CPU0: JIT: partial JIT flush (count=186) Mar 09 09:28:17.935 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608192f4 (size=2) Mar 09 09:28:17.935 CPU0: IO_FPGA: write to unknown addr 0x16, value=0x1, pc=0x608192fc (size=2) Mar 09 09:28:17.949 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:17.973 ROM: trying to read bootvar 'ROM_PERSISTENT_UTC' Mar 09 09:28:18.068 CPU0: JIT: partial JIT flush (count=188) Mar 09 09:28:18.161 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:18.236 CPU0: JIT: partial JIT flush (count=203) Mar 09 09:28:18.293 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:18.349 CPU0: JIT: partial JIT flush (count=219) Mar 09 09:28:18.438 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:18.475 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:18.522 CPU0: JIT: partial JIT flush (count=198) Mar 09 09:28:18.590 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:18.631 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:18.641 CPU0: JIT: partial JIT flush (count=217) Mar 09 09:28:18.719 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:18.817 CPU0: JIT: partial JIT flush (count=202) Mar 09 09:28:18.945 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.113 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:19.168 CPU0: JIT: partial JIT flush (count=201) Mar 09 09:28:19.235 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:19.302 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.302 CPU0: JIT: partial JIT flush (count=202) Mar 09 09:28:19.356 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:19.377 ROM: trying to set bootvar 'BSI=0' Mar 09 09:28:19.432 ROM: trying to read bootvar 'RET_2_RCALTS' Mar 09 09:28:19.432 ROM: trying to set bootvar 'RET_2_RCALTS=' Mar 09 09:28:19.481 CPU0: JIT: partial JIT flush (count=200) Mar 09 09:28:19.553 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:19.613 CPU0: JIT: partial JIT flush (count=194) Mar 09 09:28:19.661 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.679 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:19.747 CPU0: JIT: partial JIT flush (count=195) Mar 09 09:28:19.816 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:19.854 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.942 CPU0: JIT: partial JIT flush (count=183) Mar 09 09:28:19.977 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.225 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.265 CPU0: JIT: flushing data structures (compiled pages=573) Mar 09 09:28:20.462 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.711 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.796 CPU0: JIT: partial JIT flush (count=170) Mar 09 09:28:20.841 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:20.941 CPU0: JIT: partial JIT flush (count=182) Mar 09 09:28:21.020 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:21.078 CPU0: JIT: partial JIT flush (count=209) Mar 09 09:28:21.129 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:21.137 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.191 CPU0: JIT: partial JIT flush (count=197) Mar 09 09:28:21.320 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.398 VTTY: Console port is now connected (accept_fd=12,conn_fd=18) Mar 09 09:28:21.477 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.734 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.797 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:21.859 CPU0: JIT: partial JIT flush (count=211) Mar 09 09:28:21.906 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:21.984 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.047 CPU0: JIT: partial JIT flush (count=205) Mar 09 09:28:22.219 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.500 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.726 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.960 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.054 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:23.226 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.476 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.751 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.860 CPU0: JIT: partial JIT flush (count=190) Mar 09 09:28:23.985 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.235 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.485 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.730 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.761 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:24.980 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.215 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.262 CPU0: JIT: partial JIT flush (count=185) Mar 09 09:28:25.468 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.711 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.961 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.211 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.461 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:26.477 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.711 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.961 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.211 CPU0: JIT: partial JIT flush (count=182) Mar 09 09:28:27.211 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.461 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.735 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.985 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.235 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.485 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.730 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.886 CPU0: JIT: flushing data structures (compiled pages=569) Mar 09 09:28:28.964 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.058 CPU0: JIT: partial JIT flush (count=200) Mar 09 09:28:29.214 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.464 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.722 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.940 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:29.972 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.222 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.480 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.721 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.940 CPU0: JIT: partial JIT flush (count=185) Mar 09 09:28:30.987 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.205 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.487 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.713 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.744 CPU0: JIT: flushing data structures (compiled pages=569) Mar 09 09:28:31.978 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.228 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.478 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.682 CPU0: JIT: partial JIT flush (count=185) Mar 09 09:28:32.714 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.964 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.229 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.229 CPU0: JIT: flushing data structures (compiled pages=573) Mar 09 09:28:33.464 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.714 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.729 CPU0: JIT: partial JIT flush (count=169) Mar 09 09:28:33.964 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.214 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.464 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.721 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.846 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:34.987 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.206 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.487 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.713 CPU0: JIT: partial JIT flush (count=185) Mar 09 09:28:35.713 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.963 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.213 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.463 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.721 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.971 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.221 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.471 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.728 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.978 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.228 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.478 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.735 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.985 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.141 CPU0: JIT: flushing data structures (compiled pages=574) Mar 09 09:28:39.235 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.485 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.716 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.959 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.209 CPU0: JIT: partial JIT flush (count=187) Mar 09 09:28:40.209 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.459 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.709 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.959 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.052 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:41.222 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.472 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.729 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.979 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:42.057 C3745_STOP: stopping simulation. Mar 09 09:28:42.057 CPU0: CPU_STATE: Halting CPU (old state=0)... Mar 09 09:28:42.182 DEVICE: Removal of device WIC-1T(0), fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.182 VM: shutdown procedure engaged. Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "slot1" Mar 09 09:28:42.182 DEVICE: Removal of device slot1, fd=-1, host_addr=0x0, flags=2 Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "slot0" Mar 09 09:28:42.182 DEVICE: Removal of device slot0, fd=-1, host_addr=0x0, flags=2 Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "ns16552" Mar 09 09:28:42.182 DEVICE: Removal of device ns16552, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "mem_bswap" Mar 09 09:28:42.182 DEVICE: Removal of device mem_bswap, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "rom" Mar 09 09:28:42.182 DEVICE: Removal of device rom, fd=15, host_addr=0xed6c0000, flags=1 Mar 09 09:28:42.182 MMAP: unmapping of device 'rom', fd=15, host_addr=0xed6c0000, len=0x200000 Mar 09 09:28:42.182 VM_OBJECT: Shutdown of object "ram" Mar 09 09:28:42.182 DEVICE: Removal of device ram, fd=14, host_addr=0xed8c0000, flags=34 Mar 09 09:28:42.182 MMAP: unmapping of device 'ram', fd=14, host_addr=0xed8c0000, len=0x10000000 Mar 09 09:28:42.276 VM_OBJECT: Shutdown of object "gt96100" Mar 09 09:28:42.276 DEVICE: Removal of device gt96100, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.276 VM_OBJECT: Shutdown of object "io_fpga" Mar 09 09:28:42.276 DEVICE: Removal of device io_fpga, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.276 VM_OBJECT: Shutdown of object "ssa" Mar 09 09:28:42.276 DEVICE: Removal of device ssa, fd=13, host_addr=0xfd8c0000, flags=2 Mar 09 09:28:42.276 MMAP: unmapping of device 'ssa', fd=13, host_addr=0xfd8c0000, len=0x7000 Mar 09 09:28:42.276 VM_OBJECT: Shutdown of object "remote_ctrl" Mar 09 09:28:42.276 DEVICE: Removal of device remote_ctrl, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.276 VM: removing PCI busses. Mar 09 09:28:42.276 VM: deleting VTTY. Mar 09 09:28:42.276 VTTY: Console port: closing FD 12 Mar 09 09:28:42.276 VM: deleting system CPUs. Mar 09 09:28:42.276 CPU0: CPU_STATE: Halting CPU (old state=1)... Mar 09 09:28:42.276 VM: shutdown procedure completed. Mar 09 09:28:42.338 VM: trying to shutdown an inactive VM.