Mar 09 09:28:02.525 VTTY: Console port: waiting connection on tcp port 2004 for protocol IPv4 (FD 11)
Mar 09 09:28:02.588 slot0: C/H/S settings = 0/4/32
Mar 09 09:28:02.588 slot1: C/H/S settings = 0/4/32
Mar 09 09:28:02.934 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,idle_pc=0x60aa5f14,JIT on)
Mar 09 09:28:02.934 CPU0: CPU_STATE: Starting CPU (old state=2)...
Mar 09 09:28:02.950 ROM: Microcode has started.
Mar 09 09:28:02.950 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:28:02.950 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xffffffff80a9d228 (size=1)
Mar 09 09:28:02.950 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80a9d23c (size=1)
Mar 09 09:28:03.095 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x6026eef8 (size=2)
Mar 09 09:28:03.097 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60276800 (size=2)
Mar 09 09:28:03.097 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc=0x60276810 (size=2)
Mar 09 09:28:03.097 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007dac,a2=0x00000010,a3=0xbfb00000)
Mar 09 09:28:04.023 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:28:04.076 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x60283d28 (size=2)
Mar 09 09:28:04.077 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c50: bus=0,device=0,function=0,reg=0x00
Mar 09 09:28:04.077 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c54: bus=0,device=0,function=0,reg=0x00
Mar 09 09:28:04.077 CPU0: PCI: read request for device 'gt96100' at pc=0x60286a04: bus=0,device=0,function=0,reg=0x08
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x04
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x04
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x84
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x84
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:28:04.077 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:28:04.078 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=0x6028436c (size=2)
Mar 09 09:28:04.078 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:04.078 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:04.078 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.078 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:04.078 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:04.078 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:04.078 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:04.079 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x00
Mar 09 09:28:04.079 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x00
Mar 09 09:28:04.079 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x18
Mar 09 09:28:04.079 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x18
Mar 09 09:28:04.079 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x20
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x20
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x24
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x24
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x30
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x30
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x64
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x64
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x68
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x68
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:28:04.079 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x00
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x00
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x18
Mar 09 09:28:04.080 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x18
Mar 09 09:28:04.080 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x20
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x20
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x24
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x24
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x30
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x30
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x64
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x64
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x68
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x68
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x00
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x00
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x18
Mar 09 09:28:04.080 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x18
Mar 09 09:28:04.080 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x20
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x20
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x24
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x24
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x30
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x30
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.080 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x64
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x64
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x68
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x68
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.081 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60276b14 (size=2)
Mar 09 09:28:07.727 ROM: unhandled syscall 0x0000003e at pc=0x60a9e9bc (a1=0x80007d9c,a2=0x00002580,a3=0x64590000)
Mar 09 09:28:07.728 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007da4,a2=0x00000000,a3=0x64590000)
Mar 09 09:28:08.811 CPU0: JIT: partial JIT flush (count=178)
Mar 09 09:28:08.884 CPU0: JIT: flushing data structures (compiled pages=234)
Mar 09 09:28:08.943 ROM: trying to read bootvar 'BOOT'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'CONFIG_FILE'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'BOOTLDR'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'RSHELF'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'DSHELF'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'DSHELFINFO'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'RESET_COUNTER'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'CHRG_LOCRECSN'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'CHRG_ID'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'SLOTCACHE'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'OVERTEMP'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'DIAG'
Mar 09 09:28:08.943 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:28:08.967 CPU0: JIT: partial JIT flush (count=179)
Mar 09 09:28:09.093 CPU0: JIT: flushing data structures (compiled pages=242)
Mar 09 09:28:09.213 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60819334 (size=2)
Mar 09 09:28:09.213 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60818f30 (size=1)
Mar 09 09:28:09.213 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f74 (size=1)
Mar 09 09:28:09.213 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f80, value=0x00000020 (size=1)
Mar 09 09:28:09.213 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f84 (size=1)
Mar 09 09:28:09.213 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f8c, value=0x00000000 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f98 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818fa4, value=0x00000040 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fb8 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fc4, value=0x00000000 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fd0 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fe0, value=0x00000080 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adac (size=1)
Mar 09 09:28:09.214 CPU0: MTS: write access to undefined address 0x3c000002 at pc=0x6081adb8, value=0x00000080 (size=1)
Mar 09 09:28:09.214 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adbc (size=1)
Mar 09 09:28:09.382 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.531 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.676 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.830 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.978 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:10.116 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c080007 at pc=0x608190cc, value=0x00000002 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c080008 at pc=0x608190d4, value=0x00000002 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c080009 at pc=0x608190dc, value=0x00000002 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c08000a at pc=0x608190e0, value=0x00000002 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c08000b at pc=0x608190e4, value=0x00000002 (size=1)
Mar 09 09:28:10.117 CPU0: MTS: write access to undefined address 0x3c08000c at pc=0x608190e8, value=0x00000002 (size=1)
Mar 09 09:28:10.118 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60819f6c (size=1)
Mar 09 09:28:10.177 CPU0: JIT: partial JIT flush (count=187)
Mar 09 09:28:10.266 CPU0: JIT: flushing data structures (compiled pages=253)
Mar 09 09:28:10.361 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60283dd4 (size=2)
Mar 09 09:28:10.361 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000, pc=0x60283ddc (size=2)
Mar 09 09:28:10.647 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.647 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.648 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.791 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:10.791 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:10.791 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.791 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:10.791 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:10.791 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:10.791 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:11.040 CPU0: JIT: partial JIT flush (count=175)
Mar 09 09:28:11.224 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x60678648 (size=1)
Mar 09 09:28:11.224 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x60678650, value=0x00000004 (size=1)
Mar 09 09:28:11.227 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.227 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.227 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.227 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.227 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.227 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.229 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x14
Mar 09 09:28:11.234 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x14
Mar 09 09:28:11.234 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x04
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x04
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.234 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.234 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.252 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.252 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.252 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.303 CPU0: JIT: flushing data structures (compiled pages=277)
Mar 09 09:28:11.321 CPU0: IO_FPGA: read from unknown addr 0x4c, pc=0x60277d00 (size=2)
Mar 09 09:28:11.321 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0x0, pc=0x60277d08 (size=2)
Mar 09 09:28:11.322 CPU0: IO_FPGA: read from unknown addr 0x2e, pc=0x60277d28 (size=2)
Mar 09 09:28:11.322 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x40, pc=0x60277d38 (size=2)
Mar 09 09:28:11.331 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.332 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.332 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.332 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.332 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.332 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.333 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.333 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.334 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.334 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.334 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.334 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.334 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.334 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.337 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.337 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.341 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.341 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.341 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.377 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:11.434 CPU0: JIT: flushing data structures (compiled pages=281)
Mar 09 09:28:11.523 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:28:11.561 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.561 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.562 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.562 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.562 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.562 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.563 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.563 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.567 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.567 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.571 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.571 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.571 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.584 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.584 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.585 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.585 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.587 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.587 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.587 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.589 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.589 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.593 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.593 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.595 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.595 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.595 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.598 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:28:11.719 CPU0: JIT: partial JIT flush (count=201)
Mar 09 09:28:11.757 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.759 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.759 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.761 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.761 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.761 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.761 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.761 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.761 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.763 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.763 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.767 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.767 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.767 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.776 CPU0: JIT: flushing data structures (compiled pages=311)
Mar 09 09:28:12.097 CPU0: JIT: partial JIT flush (count=165)
Mar 09 09:28:12.162 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:28:12.253 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:12.318 CPU0: JIT: flushing data structures (compiled pages=310)
Mar 09 09:28:12.395 CPU0: JIT: partial JIT flush (count=202)
Mar 09 09:28:12.546 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:28:12.639 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:12.712 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:28:12.787 CPU0: JIT: partial JIT flush (count=189)
Mar 09 09:28:12.897 CPU0: JIT: flushing data structures (compiled pages=327)
Mar 09 09:28:13.007 CPU0: JIT: partial JIT flush (count=165)
Mar 09 09:28:13.268 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:28:13.340 CPU0: JIT: partial JIT flush (count=189)
Mar 09 09:28:13.868 CPU0: JIT: flushing data structures (compiled pages=555)
Mar 09 09:28:13.916 ROM: trying to read bootvar 'PMDEBUG'
Mar 09 09:28:13.929 ROM: trying to read bootvar 'MONDEBUG'
Mar 09 09:28:13.996 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:14.399 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:28:14.640 CPU0: JIT: partial JIT flush (count=193)
Mar 09 09:28:14.773 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:28:14.832 CPU0: JIT: partial JIT flush (count=213)
Mar 09 09:28:14.886 ROM: unhandled syscall 0x0000001a at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:28:14.886 ROM: unhandled syscall 0x00000009 at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:28:14.928 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:15.024 CPU0: JIT: partial JIT flush (count=194)
Mar 09 09:28:15.081 CPU0: JIT: flushing data structures (compiled pages=564)
Mar 09 09:28:15.133 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:28:15.192 CPU0: JIT: flushing data structures (compiled pages=552)
Mar 09 09:28:15.274 CPU0: JIT: partial JIT flush (count=213)
Mar 09 09:28:15.377 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:15.588 CPU0: JIT: partial JIT flush (count=180)
Mar 09 09:28:15.684 CPU0: JIT: flushing data structures (compiled pages=558)
Mar 09 09:28:15.815 CPU0: JIT: partial JIT flush (count=181)
Mar 09 09:28:15.874 CPU0: JIT: flushing data structures (compiled pages=555)
Mar 09 09:28:15.934 CPU0: JIT: partial JIT flush (count=209)
Mar 09 09:28:15.983 CPU0: JIT: flushing data structures (compiled pages=554)
Mar 09 09:28:16.043 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.094 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:28:16.163 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.254 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:28:16.333 CPU0: JIT: partial JIT flush (count=208)
Mar 09 09:28:16.336 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:16.336 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:16.337 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.337 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.337 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:16.337 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:16.338 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:16.338 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:16.343 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:16.343 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:16.343 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:16.343 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:16.343 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:16.343 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:16.345 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:16.345 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:16.391 CPU0: JIT: flushing data structures (compiled pages=558)
Mar 09 09:28:16.455 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.478 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:16.478 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:16.479 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.479 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.479 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:16.479 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:16.480 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:16.480 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:16.505 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:28:16.594 CPU0: JIT: partial JIT flush (count=204)
Mar 09 09:28:16.657 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:16.709 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:28:16.764 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:28:16.830 CPU0: JIT: partial JIT flush (count=203)
Mar 09 09:28:16.905 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:16.929 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:16.929 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:16.929 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:16.973 CPU0: JIT: partial JIT flush (count=219)
Mar 09 09:28:17.029 CPU0: JIT: flushing data structures (compiled pages=558)
Mar 09 09:28:17.082 CPU0: JIT: partial JIT flush (count=216)
Mar 09 09:28:17.153 CPU0: JIT: flushing data structures (compiled pages=573)
Mar 09 09:28:17.206 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:28:17.225 CPU0: JIT: partial JIT flush (count=197)
Mar 09 09:28:17.480 CPU0: JIT: flushing data structures (compiled pages=570)
Mar 09 09:28:17.539 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608192f4 (size=2)
Mar 09 09:28:17.539 CPU0: IO_FPGA: write to unknown addr 0x16, value=0x1, pc=0x608192fc (size=2)
Mar 09 09:28:17.547 CPU0: JIT: partial JIT flush (count=196)
Mar 09 09:28:17.564 ROM: trying to read bootvar 'ROM_PERSISTENT_UTC'
Mar 09 09:28:17.665 CPU0: JIT: flushing data structures (compiled pages=567)
Mar 09 09:28:17.743 CPU0: JIT: partial JIT flush (count=197)
Mar 09 09:28:17.799 CPU0: JIT: flushing data structures (compiled pages=567)
Mar 09 09:28:17.854 CPU0: JIT: partial JIT flush (count=216)
Mar 09 09:28:17.938 CPU0: JIT: flushing data structures (compiled pages=567)
Mar 09 09:28:17.993 CPU0: JIT: partial JIT flush (count=216)
Mar 09 09:28:18.058 CPU0: JIT: flushing data structures (compiled pages=566)
Mar 09 09:28:18.079 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.267 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:18.342 CPU0: JIT: flushing data structures (compiled pages=566)
Mar 09 09:28:18.440 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.544 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:18.609 CPU0: JIT: flushing data structures (compiled pages=575)
Mar 09 09:28:18.703 CPU0: JIT: partial JIT flush (count=192)
Mar 09 09:28:18.752 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.755 ROM: trying to set bootvar 'BSI=0'
Mar 09 09:28:18.767 ROM: trying to read bootvar 'RET_2_RCALTS'
Mar 09 09:28:18.767 ROM: trying to set bootvar 'RET_2_RCALTS='
Mar 09 09:28:18.773 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:28:18.846 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:18.890 CPU0: JIT: flushing data structures (compiled pages=570)
Mar 09 09:28:18.958 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:18.990 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.030 CPU0: JIT: flushing data structures (compiled pages=570)
Mar 09 09:28:19.116 CPU0: JIT: partial JIT flush (count=204)
Mar 09 09:28:19.191 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.315 CPU0: JIT: flushing data structures (compiled pages=566)
Mar 09 09:28:19.448 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.482 CPU0: JIT: partial JIT flush (count=183)
Mar 09 09:28:19.640 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:19.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.766 CPU0: JIT: partial JIT flush (count=192)
Mar 09 09:28:19.877 CPU0: JIT: flushing data structures (compiled pages=567)
Mar 09 09:28:19.945 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.232 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.300 CPU0: JIT: partial JIT flush (count=170)
Mar 09 09:28:20.452 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.696 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.852 CPU0: JIT: flushing data structures (compiled pages=575)
Mar 09 09:28:20.960 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.217 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.461 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.687 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.969 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.219 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.437 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.726 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.944 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.194 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.444 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.673 CPU0: JIT: partial JIT flush (count=196)
Mar 09 09:28:23.688 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.938 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.188 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.438 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.715 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.933 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.246 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.293 CPU0: JIT: flushing data structures (compiled pages=571)
Mar 09 09:28:25.452 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.696 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.946 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.196 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.446 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.696 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.946 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.196 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.446 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.688 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.938 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.188 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.438 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.579 CPU0: JIT: partial JIT flush (count=188)
Mar 09 09:28:28.714 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.949 CPU0: JIT: flushing data structures (compiled pages=573)
Mar 09 09:28:28.949 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.199 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.449 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.956 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.018 CPU0: JIT: partial JIT flush (count=198)
Mar 09 09:28:30.206 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.464 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.690 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.940 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.190 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.440 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.697 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.947 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.228 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.447 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.698 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.948 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.198 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.323 CPU0: JIT: flushing data structures (compiled pages=575)
Mar 09 09:28:33.448 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.698 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.948 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.198 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.386 CPU0: JIT: partial JIT flush (count=191)
Mar 09 09:28:34.448 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.956 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.206 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.456 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.713 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.963 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.213 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.463 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.689 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.939 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.221 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.471 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.697 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.947 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.197 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.447 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.610 CPU0: JIT: flushing data structures (compiled pages=573)
Mar 09 09:28:38.688 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.954 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.204 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.376 CPU0: JIT: partial JIT flush (count=198)
Mar 09 09:28:39.454 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.716 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.943 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.193 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.349 CPU0: JIT: flushing data structures (compiled pages=574)
Mar 09 09:28:40.443 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.693 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.943 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.206 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.456 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.713 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.963 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:42.057 C3745_STOP: stopping simulation.
Mar 09 09:28:42.057 CPU0: CPU_STATE: Halting CPU (old state=0)...
Mar 09 09:28:42.151 DEVICE: Removal of device WIC-1T(0), fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.151 VM: shutdown procedure engaged.
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "slot1"
Mar 09 09:28:42.151 DEVICE: Removal of device slot1, fd=-1, host_addr=0x0, flags=2
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "slot0"
Mar 09 09:28:42.151 DEVICE: Removal of device slot0, fd=-1, host_addr=0x0, flags=2
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "ns16552"
Mar 09 09:28:42.151 DEVICE: Removal of device ns16552, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "mem_bswap"
Mar 09 09:28:42.151 DEVICE: Removal of device mem_bswap, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "rom"
Mar 09 09:28:42.151 DEVICE: Removal of device rom, fd=14, host_addr=0xed800000, flags=1
Mar 09 09:28:42.151 MMAP: unmapping of device 'rom', fd=14, host_addr=0xed800000, len=0x200000
Mar 09 09:28:42.151 VM_OBJECT: Shutdown of object "ram"
Mar 09 09:28:42.151 DEVICE: Removal of device ram, fd=13, host_addr=0xeda00000, flags=34
Mar 09 09:28:42.151 MMAP: unmapping of device 'ram', fd=13, host_addr=0xeda00000, len=0x10000000
Mar 09 09:28:42.229 VM_OBJECT: Shutdown of object "gt96100"
Mar 09 09:28:42.229 DEVICE: Removal of device gt96100, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.229 VM_OBJECT: Shutdown of object "io_fpga"
Mar 09 09:28:42.229 DEVICE: Removal of device io_fpga, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.229 VM_OBJECT: Shutdown of object "ssa"
Mar 09 09:28:42.229 DEVICE: Removal of device ssa, fd=12, host_addr=0xfda00000, flags=2
Mar 09 09:28:42.229 MMAP: unmapping of device 'ssa', fd=12, host_addr=0xfda00000, len=0x7000
Mar 09 09:28:42.229 VM_OBJECT: Shutdown of object "remote_ctrl"
Mar 09 09:28:42.229 DEVICE: Removal of device remote_ctrl, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.229 VM: removing PCI busses.
Mar 09 09:28:42.229 VM: deleting VTTY.
Mar 09 09:28:42.229 VTTY: Console port: closing FD 11
Mar 09 09:28:42.229 VM: deleting system CPUs.
Mar 09 09:28:42.229 CPU0: CPU_STATE: Halting CPU (old state=1)...
Mar 09 09:28:42.244 VM: shutdown procedure completed.
Mar 09 09:28:42.307 VM: trying to shutdown an inactive VM.